Video signal sampling apparatus

ABSTRACT

A video signal sampling apparatus for sampling an input analog video signal by use of a sampling clock, and producing a digital signal which represents a level of a resultant video signal sample as a digital video signal is disclosed. The video signal sampling apparatus includes N (N being an integer equal to or greater than 2) converters for sampling the input analog video signal by use of N sampling clocks having phases that are different from each other to produce N digital signals which represent levels of N resultant video signal samples respectively, and a selector for selecting one digital signal from the N digital signals produced by the N converters in order that an amplitude of the digital video signal output to the outside is maximized.

FIELD OF THE INVENTION

[0001] The present invention relates to a video signal samplingapparatus used for converting an analog video signal into a digitalvideo signal.

BACKGROUND OF THE INVENTION

[0002] A sampling clock of a certain sampling frequency is needed forperforming a sampling process for converting an analog signal into adigital signal. Generally, to convert an analog video signal into adigital video signal, a sampling clock in synchronization with ahorizontal sync signal or a vertical sync signal is used.

[0003] According to Nyquist's theorem, when a sampling frequency is fsc,if the highest frequency component of an input signal is lower thanfsc/2, information on waveforms of the input signal is not lost, thatis, original waveforms of the input signal can be reproduced withperfection. However, this holds only when the input signal and thesampling clock are in an optimum condition in terms of their phases.

[0004] The reason for this will be explained with reference to FIGS. 8and 9 below. FIG. 8 shows an input signal A_(in) of a constant frequencyand an output signal (a sample) A_(out) obtained by sampling the inputsignal A_(in) by use of a sampling clock A_(clk) which has a frequencythat is twice that of the input signal A_(in), and is in an optimumphase relation with the input signal A_(in). When the input signal Ai issampled by use of this optimum sampling clock A_(clk), differencebetween the highest level and the lowest level, that is, the amplitudeof a resultant output signal representing its AC component is at itsmaximum as apparent from FIG. 8.

[0005]FIG. 9 shows the same input signal A_(in) and an output signalBout obtained by sampling this same input signal A_(in) by use of asampling clock B_(clk) which is 180° (π radians) out of phase with thesampling clock A_(clk). When the input signal A_(in) is sampled by useof this sampling clock B_(clk) that is most distant from the optimumsampling clock A_(clk), the amplitude (AC component) of a resultantoutput signal is at its minimum (zero) as apparent form FIG. 9. Asdescribed above, if the same input signal is sampled, the amplitude of aresultant output signal varies depending on a phase of a sampling clock.It is also well known that the variation range of the amplitude of anoutput signal obtained by sampling an input signal depends on thefrequency of a sampling clock as shown in FIG. 10.

[0006] In the graph of FIG. 10, the horizontal axis represents afrequency of an input signal, and the vertical axis represents anamplitude (its maximum value is normalized to 1) of an output signalobtained by sampling the input signal by use of a sampling clock of afrequency fsc. The curve C_(max) represents amplitudes of the outputsignal when the input signal and the sampling clock are in the optimumphase relation, the curve C_(min) represents amplitudes of the outputsignal when they are most distant from the optimum phase relation, andthe curve Cave represents average amplitudes of the output signal. Fromthis graph, it is apparent that the amplitude of the output signalvaries widely depending on the phase of the sampling clock not only whenthe frequency fsc of the sampling clock is twice that of the inputsignal, but also when it is three or four times that of the inputsignal.

OBJECT AND SUMMARY OF THE INVENTION

[0007] Accordingly, if the phase of the sampling clock shifts, theamplitude of the output signal (digital video signal) obtained bysampling the input signal varies, which degrades image quality. Thisimage quality degradation occurs not only when a received NTSC analogvideo signal is converted into a digital video signal, but also when avideo signal output from a solid image pickup device such as a CCD issampled. Not alone a display apparatus using a CRT, but a matrix typedisplay apparatus such as an LCD or a PDP (Plasma Display) involves sucha problem.

[0008] The present invention has been made to solve the above-describedproblem with an object of providing a video signal sampling apparatuscapable of outputting a digital video signal that has always anamplitude almost equal to its maximum value (an amplitude of the outputsignal obtained when an input signal and a sampling clock are in theoptimum phase relation) irrespective of the phase of the sampling clock.

[0009] The above-described object is achieved by a video signal samplingapparatus for sampling an input analog video signal by use of a samplingclock, and producing a digital signal representing a level of aresultant video signal sample as a digital video signal to be output tothe outside, said apparatus comprising:

[0010] N (N being an integer equal to or greater than 2) converters forsampling the input analog video signal by use of N sampling clockshaving phases that are different from each other to produce N digitalsignals which represent levels of N resultant video signal samplesrespectively;

[0011] a selector for selecting one digital signal from the N digitalsignals produced by said N converters in order that an amplitude of thedigital video signal output to the outside is maximized; and

[0012] a switching device for outputting said one digital signalselected by said selector to the outside as the digital video signal.

[0013] The selector may have a processor for calculating, for each ofthe N digital signals produced by said N converters, a differencebetween a value at current sampling and a value at preceding sampling,and for selecting, from said N digital signals, one digital signal thathas a maximum absolute value of said difference.

[0014] The video signal sampling apparatus may further comprise delayelements connected in series for delaying a reference sampling clock by2π/N radians in succession to produce said N sampling clocks to besupplied to said N converters.

[0015] The video signal sampling apparatus may further comprise a mixerfor mixing the digital video signal output from said switching devicewith one of said N digital signals produced by said N converters.

[0016] The above-described object is also achieved by a video signalsampling apparatus for sampling an input analog video signal by use of asampling clock, and producing a digital signal which represents a levelof a resultant video signal sample as a digital video signal to beoutput to the outside, said apparatus comprising:

[0017] a converter for sampling the input analog video signal by use ofa sampling clock to produce a digital signal representing a level of aresultant video signal sample;

[0018] a selector for selecting one digital signal from a group of afirst to N-th (N being an integer equal to or greater than 2)consecutive digital signals output from said converter in order that anamplitude of the digital video signal output to the outside ismaximized; and

[0019] a switching device for outputting said one digital signalselected by said selector to the outside as the digital video signal.

[0020] The selector may have a processor for calculating, for each ofsaid first to N-th digital signals output from said converter, adifference between a value at current sampling and a value at precedingsampling, and for selecting, from said N digital signals, one digitalsignal that has a maximum absolute value of said difference.

[0021] The video signal sampling apparatus may further comprise (N−1)delay element or elements for delaying output of said converter by onesampling clock pulse to (N−1) sampling clock pulses respectively toproduce said first to N-th digital signals.

[0022] The video signal sampling apparatus may further comprise a sampleand hold circuit for decimating samples output from said switchingdevice to 1/N.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Embodiments of the invention will now be described by way ofexample and with reference to the accompanying drawings in which:

[0024]FIG. 1 is a block diagram showing a structure of a first exampleof the video signal sampling apparatus according to the invention;

[0025]FIG. 2 is a block diagram showing a structure of the first examplein a case where the number of A/D converters is 2 (N=2)

[0026]FIG. 3 is a view showing a structure of a selector used in thefirst example;

[0027]FIG. 4 is a view explaining the operation of the first example;

[0028]FIG. 5 is a block diagram showing a structure of a second exampleof the video signal sampling apparatus according to the invention;

[0029]FIG. 6 is a view showing a structure of a selector used in thesecond example;

[0030]FIG. 7 is a block diagram showing a structure of a third exampleof the video signal sampling apparatus according to the invention;

[0031]FIG. 8 is a view showing a phase relation between an input signaland a sampling clock when the amplitude of an output signal is at itsmaximum;

[0032]FIG. 9 is a view showing a phase relation between the input signaland the sampling clock when the amplitude of the output signal is at itsminimum; and

[0033]FIG. 10 is a graph for explaining how an amplitude of an outputsignal (a sample) is affected by a frequency and a phase of a samplingclock.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034]FIG. 1 is a block diagram showing a structure of a first exampleof the video signal sampling apparatus according to the invention. Asshown in FIG. 1, the apparatus of the first example has a first to N-th(N is an integer equal to or greater than two) AID converters(analog-to-digital converters) AD₁ to AD_(N), delay elements PD₁ toPD_(N-1) connected to the second to N-th A/D converters AD₂ to AD_(N)respectively, a switching device 1, and a selector 2.

[0035] The A/D converters AD₁ to AD_(N) sample an input video signal andproduce digital data which represent levels of resultant video signalsamples. The delay elements PD₁, PD₂, . . . , PD_(N−1)delay a samplingclock by 1·2π/N, 2·2π/ N, . . . , (N−1)·2π/N radians respectively.Accordingly, the times at which the AID converters AD₂ to AD_(N) producedigital data are delayed from the time at which the A/D converter AD₁produces digital data by 1·2π/N, 2·2π/N, . . . , (N−1)·2 π/N radiansrespectively. The selector 2 selects from among digital data output fromthe A/D converters AD₁ to AD_(N) in accordance with an after-describedprocedure. The switching device 1 outputs digital data selected by theselector 2 to the outside as a digital video signal.

[0036] The operation of the apparatus of the first example will now bedescribed below. Here, to simplify explanation, assume that N=2, thatis, assume that the apparatus has two A/D converters and one delayelement. FIG. 2 shows a structure of the apparatus of the first examplein this case. In this structure, the delay element PD₁ delays thesampling clock by π radians.

[0037]FIG. 3 shows a structure of the selector 2 in this case. In FIG.3, 21 denotes a delay circuit for delaying digital data DATA(A) outputfrom the A/D converter AD₁ by one clock pulse, 22 denotes a subtracterfor producing a difference between the digital data DATA (A) output fromthe A/D converter AD₁ and another digital data DATA(A) delayed by oneclock pulse and output from the delay circuit 21, that is, thedifference between the current data and the preceding data, and 23denotes an absolute-value processor for producing an absolute value ofan output of the subtracter 22. 24 denotes a delay circuit for delayingdigital data DATA (B) output from the A/D converter AD₂ by one clockpulse, 25 denotes a subtracter for producing a difference between thedigital data DATA (B) output from the A/D converter AD₂ and anotherdigital data DATA(B) delayed by one clock pulse and output from thedelay circuit 24, that is, the difference between the current data andthe preceding data, and 26 denotes an absolute-value processor forproducing an absolute value of an output of the subtracter 25. 27denotes a selection signal generator which compares an output of theabsolute-value processor 23 with that of the absolute-value processor26, generates a selection signal SEL used for determining which of DATA(A) and DATA(B) should be output to the outside on the basis of theresult of the comparison, and supplies the selection signal SEL to theswitching device 1.

[0038] Here, assume that the A/D converter AD₁ samples an input videosignal at times A1, A2, A3, A4 . . . . , and outputs digital data A1,A2, A3, A4 . . . . , and that the A/D converter AD₂ samples the sameinput video signal at times B1, B2, B3, B4 . . . . , and outputs digitaldata B1, B2, B3, B4 . . . . , as shown in FIG. 4.

[0039] In this case, as is apparent from FIG. 4, since |B2-B1|>|A2-A1|,the selector 2 selects the data B2 from a pair of the data A2 and thedata B2. Likewise, the selector 2 selects the data B3 from a pair of thedata A3 and the data B3, and selects the data B4 from a pair of the dataA4 and the data B4. The switching device 1 outputs the data B1, B2, B3,B4 . . . . as a digital video signal to the outside in accordance withthis selection made by the selector 2.

[0040] In the above-described example, the digital video signal outputfrom the switching device 1 does not necessarily have a maximumamplitude (the amplitude of the digital video signal output when theinput signal and the sampling clock are in the optimum phase relation),since the amplitude depends on the phase of the sampling clock. However,it is at least larger than the average amplitude Cave described withreference to FIG. 10, since the phases of the sampling clocks suppliedto the two A/D converters are distant from each other by π radians. If Nis increased, that is, if the number of the A/D converters is increased,it is possible to output a digital video signal whose amplitude isalways almost at its maximum irrespective of the phases of the samplingclocks.

[0041]FIG. 5 is a block diagram showing a structure of a second exampleof the video signal sampling apparatus according to the invention. InFIG. 5, reference numerals identical to those in FIG. 2 represent thesame elements.

[0042] The second example is characterized in that, in order to dispensewith the A/D converter AD₂, the frequency of the sampling clock isdoubled and a delay element 3 for delaying the output of the A/Dconverter A/D₁ by one clock pulse is used instead of the delay elementPD₁for delaying the sampling clock by π radians. In this structure, asis the case with the first example, the data A1, A2, A3, A4 . . . . ,and the data B1, B2, B3, B4, . . . . are supplied to a selector 20 fromthe A/D converter AD₁ and the delay element 3 respectively. However, inthis second example, the switching device 1 has to be provided with asample and hold circuit 4 for reducing the samples output therefrom inhalf, since the frequency of the sampling clock is doubled.

[0043]FIG. 6 shows a structure of the selector 20 used in the secondexample. The selector 20 has the same structure as the selector 2 usedin the first example except that the selector 20 has delay circuits 28and 29 for delaying DATA(A) and DATA(B) by two clock pulses respectivelyinstead of the delay circuits 21 and 24 for delaying DATA(A) and DATA(B)by one clock pulse respectively. The selector 20 operates in the samemanner as the selector 2.

[0044] Although the second example has the sample and hold circuit 4 forreducing samples being output to the outside in half, it is possible tofrequency-divide the sampling clock in half to produce another samplingclock and to drive the switching device 1 and the selector 20 with thisfrequency-divided sampling clock. With this arrangement, the sample andhold circuit 4 can be dispensed with.

[0045]FIG. 7 is a block diagram showing a structure of a third exampleof the video signal sampling apparatus according to the invention. InFIG. 7, reference numerals identical to those in FIG. 1 represent thesame elements.

[0046] The third example is characterized in that a mixer 5 is providedat the output of the switching device 1. As apparent from the graph ofFIG. 10, the range of amplitude variation of an output video signal,which depends on a phase relation between an input video signal and asampling clock, increases as the frequency of the input video signalincreases. In the third example, the mixer 5 mixes the signal outputform the switching device 1 with one of the signals output from the A/Dconverters AD₁ to AD_(N). The mixer 1 has an adjustable mixing ratio,and therefore, with this third example, it is possible to adjust levelsof high-frequency components of the output video signal to improve imagequality.

[0047] The above explained preferred embodiments are exemplary of theinvention of the present application which is described solely by theclaims appended below. It should be understood that modifications of thepreferred embodiments may be made as would occur to one of skill in theart.

1. A video signal sampling apparatus for sampling an input analog videosignal by use of a sampling clock, and producing a digital signalrepresenting a level of a resultant video signal sample as a digitalvideo signal to be output to the outside, said apparatus comprising: N(N being an integer equal to or greater than 2) converters for samplingthe input analog video signal by use of N sampling clocks having phasesthat are different from each other to produce N digital signals whichrepresent levels of N resultant video signal samples respectively; aselector for selecting one digital signal from the N digital signalsproduced by said N converters in order that an amplitude of the digitalvideo signal output to the outside is maximized; and a switching devicefor outputting said one digital signal selected by said selector to theoutside as the digital video signal.
 2. A video signal samplingapparatus according to claim 1, in which said selector has a processorfor calculating, for each of the N digital signals produced by said Nconverters, a difference between a value at current sampling and a valueat preceding sampling, and for selecting, from said N digital signals,one digital signal that has a maximum absolute value of said difference.3. A video signal sampling apparatus according to claim 1, furthercomprising delay elements connected in series for delaying a referencesampling clock by 2 π/N radians in succession to produce said N samplingclocks to be supplied to said N converters.
 4. A video signal samplingapparatus according to claim 1, further comprising a mixer for mixingthe digital video signal output from said switching device with one ofsaid N digital signals produced by said N converters.
 5. A video signalsampling apparatus for sampling an input analog video signal by use of asampling clock, and producing a digital signal which represents a levelof a resultant video signal sample as a digital video signal to beoutput to the outside, said apparatus comprising: a converter forsampling the input analog video signal by use of a sampling clock toproduce a digital signal representing a level of a resultant videosignal sample; a selector for selecting one digital signal from a groupof a first to N-th (N being an integer equal to or greater than 2)consecutive digital signals output from said converter in order that anamplitude of the digital video signal output to the outside ismaximized; and a switching device for outputting said one digital signalselected by said selector to the outside as the digital video signal. 6.A video signal sampling apparatus according to claim 5, in which saidselector has a processor for calculating, for each of said first to N-thdigital signals output from said converter, a difference between a valueat current sampling and a value at preceding sampling, and forselecting, from said N digital signals, one digital signal that has amaximum absolute value of said difference.
 7. A video signal samplingapparatus according to claim 5, further comprising (N−1) delay elementor elements for delaying output of said converter by one sampling clockpulse to (N−1) sampling clock pulses respectively to produce said firstto N-th digital signals.
 8. A video signal sampling apparatus accordingto claim 5, further comprising a sample and hold circuit for decimatingsamples output from said switching device to 1/N.